Increasingly, resistive RAM (ReRAM) devices and dynamic RAM (DRAM) devices are being used in mobile devices such as mobile phones and tablets due to their reduced power consumption and straightforward fabrication. Each of these devices comprises a plurality of memory cells forming an array of memory to store data. Conventionally, the memory cells are formed using a combination of one transistor and either one resistor or one capacitor. Generally, this architecture is referred to as “1T1R” or “1T1C”. In the 1T1R or 1T1C architecture, the resistor or capacitor is often formed under a bitline, where the bitline is used to sense, program and reset a memory cell. In some instances, the resistor or capacitor is formed over the bitline at the cost of reduced operational speed. Forming the resistance or capacitance under the bitline may however increase the size of memory cells because the bitline contact must be formed between the resistor or capacitor. To address this problem, self-aligned contact technology is widely used in minimizing the wiring space and locating the contact among the wiring itself. The self-aligned contact technology (generally used in forming R or C below the bitline) is generally used when forming memory from a subtract structure. However, forming the self-aligned contact via etching processes causes damage to side portions of the material used to form the memory structure.
The use of a damascene structure in forming a memory device allows manufacturers to avoid damage to the side portion of the material. However, the damascene structure makes it difficult to isolate the resistor or capacitor with respect to the bitline contact, thus making it difficult to form a self-aligned contact.
Therefore, there is a need in the art for a method of forming a self-aligned contact within a damascene structure and process in accordance with exemplary embodiments of the present invention.